This invention relates in general to flash analog-to-digital converters ("ADCs") and in particular, to a technique and circuit for connecting a least-significant-bits ("LSB") reference ladder to a most-significant-bits ("MSB") reference ladder in a two-step flash ADC (also referred to as a "half-flash ADC").
The two-step flash ADC provides much of the same speed advantages as a one-step flash ADC (also referred to as a "full flash ADC") as compared to, for examples, dual-slope and successive approximation ADCs, while its design is considerably less complex than that of the one-step flash ADC. In particular, whereas a one-step flash ADC requires 2.sup.n -1 comparators for n-bit resolution, a two-step flash ADC only requires 2.sup.n/2+1 -1 comparators. Since fewer comparators are required, the die size of an integrated circuit implementing a two-step flash ADC can be considerably smaller than that of an integrated circuit implementing a one-step flash ADC of comparable bit resolution and as a result, its manufacturing cost may be considerably less. Also, since fewer comparators are required, the power consumption of an integrated circuit implementing a two-step flash ADC may be considerably less than that for an integrated circuit implementing a one-step flash ADC of comparable resolution.
FIG. 1 is useful for illustrating the basic operation of a two-step flash ADC. In particular, a MSB reference ladder 12 and its corresponding MSB comparators CM01-CM15, a LSB reference ladder 14 and its corresponding LSB comparators CL01-CL16, a MSB decoder logic circuit 16 for processing the outputs of the MSB comparators CM01-CM15, a connection logic circuit 18 for connecting the LSB reference ladder 14 across a selected portion of the MSB reference ladder 12, a LSB decoder logic circuit 20 for processing the outputs of the LSB comparators CL01-CL16, and a carryover logic circuit 28 for generating the digital output of the two-step flash ADC are shown. The MSB reference ladder 12 includes a plurality of equal-valued resistors RM01-RM16 (each having a resistance value of RM) serially connected together between a reference voltage Vref and ground GND to form a voltage divider circuit providing MSB reference voltages VM01-VM15 at respective nodes NM01-NM15 of the MSB reference ladder 12. The LSB reference ladder 14 also includes a plurality of equal-valued resistors RL01-RL16 serially connected together between selected adjacent nodes of the MSB reference ladder 12 to form a second voltage divider circuit having a total resistance of R.sub.L and providing LSB reference voltages VL01-VL16 at respective nodes NL01-NL16 of the LSB reference ladder 14.
In a first step of the two-step flash ADC, a gross resolution of the analog input voltage Vin is conducted by simultaneously comparing the input voltage Vin against each of the MSB reference voltages VM01-VM15. In particular, each of the MSB comparators CM01-CM15 receives and compares the input voltage Vin against a corresponding one of the MSB reference voltages VM01-VM15, and generates an output as a result of that comparison. The respective outputs TM01-TM15 of the MSB comparators CM01-CM15 resemble a so-called "thermometer" output in that each output corresponding to a MSB reference voltage less than the input voltage Vin is HIGH, and each output corresponding to a MSB reference voltage greater than or equal to the input voltage Vin is LOW. Where the thermometer outputs TM01-TM15 of the MSB comparators CM01-CM15 transition from a HIGH to a LOW output, the input voltage Vin is determined to be either somewhere in between the two MSB reference voltages corresponding to the HIGH to LOW transition outputs, or equal to the higher of the two MSB reference voltages corresponding to the HIGH to LOW transition outputs. The MSB decoder logic circuit 16 receives the thermometer outputs TM01-TM15, and decodes them to generate the four most-significant-bits 24 of an 8-bit binary number representing the analog input voltage Vin and to generate control signals 22 provided to the connect logic circuit 18.
In a second step of the two-step flash ADC, a finer resolution of the analog input voltage Vin is conducted by connecting the LSB reference ladder 14 across the two MSB reference voltages corresponding to the previously determined HIGH to LOW transition outputs of the MSB comparators CM01-CM15, and comparing the input voltage Vin against each of the LSB reference voltages VL01-VL16. The respective outputs TL01-TL16 of the LSB comparators CL01-CL16 also resemble a so-called "thermometer" output in that each of the outputs corresponding to a LSB reference voltage less than the input voltage Vin is HIGH, and each of the outputs corresponding to a LSB reference voltage greater than the input voltage Vin is LOW. Where the thermometer outputs TL01-TL16 of the LSB comparators CL01-CL16 transition from a HIGH to a LOW output, the input voltage Vin is determined to be either somewhere in between the two LSB reference voltages corresponding to the HIGH to LOW transition outputs, or equal to the higher of the two LSB reference voltages corresponding to the HIGH to LOW transition outputs. The LSB decoder logic circuit 20 receives the thermometer outputs TL01-TL16, and decodes them to generate the four least-significant-bits 26 of the 8-bit binary number representing the analog input voltage Vin. The 8-bit binary number representing the analog input voltage Vin is then generated by the carryover logic circuit 28 from the four most-significant-bits 24 from the MSB decoder logic circuit 16 and the four least-significant-bits 26 from the LSB decoder logic circuit 20. Except for the case where all sixteen outputs TL01-TL16 of the LSB comparators CL01-CL16 are HIGH, the carryover logic circuit 28 generates the 8-bit binary number representing the analog input voltage Vin by merely combining the four most-significant-bits 24 from the MSB decoder logic circuit 16 with the four least-significant-bits 26 from the LSB decoder logic circuit 20. For example, if the four most-significant-bits 24 from the MSB decoder logic circuit 16 are respectively HIGH, HIGH, LOW, and LOW (i.e., 1100), and the four least-significant-bits 26 from the LSB decoder logic circuit 20 are respectively LOW, HIGH, LOW, and LOW (i.e., 0100), then the 8-bit binary number generated by the carryover logic circuit 28 would be 11000100. In the case where all sixteen outputs TL01-TL16 of the LSB comparators CL01-CL16 are HIGH, however, the carryover logic circuit 28 generates the 8-bit binary number representing the analog input voltage Vin by incrementing the four most-significant-bits 24 from the MSB decoder logic circuit 16 by one and setting each of the four least-significant-bits 26 from the LSB decoder logic circuit 20 to LOW. For example, if the four most-significant-bits 24 from the MSB decoder logic circuit 16 are 1100, and all sixteen outputs TL01-TL16 of the LSB comparators CL01-CL16 are HIGH, then the 8-bit binary number generated by the carryover logic circuit 28 would be 11010000.
FIG. 2 illustrates an example of the MSB reference ladder 12, the LSB reference ladder 14, and the connection logic circuit 18. The MSB reference ladder 12 comprises sixteen equal-valued resistors RM01-RM16 connected in series between Vref and ground GND to form a voltage divider circuit. The LSB reference ladder 14 comprises sixteen passgates RL01-RL16 also connected in series to form a voltage divider circuit, wherein each of the passgates RL01-RL16 acts as a high valued resistor by always being turned ON. The connection logic circuit 18 comprises passgates P1-P16 and P1'-P16', wherein passgate pairs are formed by pairing unprimed and primed passgates having the same numbers (e.g., P1 and P1'). The LSB reference ladder 14 is connected across adjacent nodes of the MSB reference ladder 12 by selectively turning ON one of the passgate pairs P1/P1'-P16/P16', while turning OFF all other passgate pairs. For example, to connect the LSB reference ladder 14 across nodes NM14 and NM15 of the MSB reference ladder 12, control signals C15' and C15 from the MSB decoder logic circuit 16 would turn 0N their respective passgates P15' and P15, while control signals C1'-C14', C16', C1-C14, and C16 from the MSB decoder logic circuit 16 would turn OFF their respective passgates P1'-P14', P16', P1-P14, and P16.
FIGS. 3A and 3B are useful for illustrating one problem with the two-step flash ADC as described in reference to FIG. 1. When the LSB reference ladder 14 is connected across two adjacent nodes NM(k-2) and NM(k-1) of the MSB reference ladder 12, the LSB reference ladder 14 tends to disturb the MSB reference ladder 12. In particular, the effective resistance RM' across the two adjacent nodes NM(k-2) and NM(k-1) of the MSB reference ladder 12 changes from a value of RM to another value equal to RM in parallel with R.sub.L, where R.sub.L is the total resistance of the LSB reference ladder 14. As a consequence, the differential voltage between the MSB reference voltages VM(k-2) and VM(k-1), respectively corresponding to nodes NM(k-2) and NM(k-1), is different than that between all other MSB reference voltages on the MSB reference ladder 12, causing a slight measurement error in the two-step flash ADC described. For example, the differential voltage between the MSB reference voltages VM(k-2) and VM(k-1) is: ##EQU1## whereas the differential voltage between all other MSB reference voltages is: EQU .DELTA.V=I*RM (2)
where I is equal to the current flowing through the MSB reference ladder 12, and RM is the resistance value of each of the equal-valued resistors RM01-RM16. Consequently, if RM is equal to 200.OMEGA. and R.sub.L is equal to 3,200.OMEGA., then the differential voltage between the MSB reference voltages VM(k-2) and VM(k-1) would be approximately equal to I*188.OMEGA., whereas the differential voltage between all other MSB reference voltages would be equal to I*200.OMEGA..
U.S. Pat. No. 4,571,574, incorporated herein by this reference, describes one technique of avoiding the above described LSB reference ladder connection problem by employing a LSB reference ladder having the same resistance value as each MSB resistor of a MSB reference ladder, and switchably replacing one of the MSB resistors connected across two adjacent nodes of the MSB reference ladder with the LSB reference ladder when connecting the LSB reference ladder across the two adjacent nodes. The switching means required for such switchable replacement, however, significantly adds to the complexity of such integrated circuits.